1. Field of the Invention
The present invention relates to a data input apparatus of a DDR SDRAM and a method thereof, and more particularly to, a data input apparatus of a DDR SDRAM and a method capable of correctly arranging an input control signal and a data input operation.
2. Discussion of Related Art
As well known, DRAM among semiconductor memory devices has used a synchronous DRAM (hereinafter, SDRAM) operated in synchronization with an external system clock in order to improve an operation speed. On the other hand, a general SDRAM is a device inputting/outputting one data for a cycle period by synchronizing with a rising edge of a clock, while DDR SDRAM can input/output two data in sequence by synchronizing with rising and falling edges of the clock. Accordingly, without increasing a frequency of a clock, the DDR SDRAM has been considered as a next generation DRAM by means of embodying an operation speed two times as fast as the conventional SDRAM.
FIG. 1 is a block diagram illustrating a data input path of DDR SDRAM of the conventional art.
Referring to FIG. 1, a data input path of the DDR SDRAM is comprised of: a data strobe buffer 110 for buffering a data strobe signal DQS in response to an enable signal endindsb; a data strobe signal division unit 120 for generating a rising edge detecting pulse signal rdinclk and a falling edge detecting pulse signal fdinclk by dividing a signal outputted from the data strobe buffer 110; a data input buffer 130 for buffering an input data inputted from an input terminal DQ in response to the enable signal endindsb; a rising data latch 141 for latching the input data DIN outputted from the data input buffer 130 in response to the rising edge detecting pulse signal rdinclk; a falling data latch 142 for outputting a data as a falling data dinf by latching the input data DIN outputted from the data input buffer 130 in response to the falling edge detecting pulse signal fdinclk; a data arranging unit 150 for outputting a data dunr6 as a rising data dinr by arranging a falling data dinf with the data dinr6 outputted from the rising data latch 141 in response to the falling edge detecting pulse signal fdinclk; an input control signal generation unit 170 for generating a data input strobe pulse dinstbp in response to a clock signal pulse clkp2 and a control signal soseb_wt deciding a data outputted earlier than the other of an even data and an odd data; a global input/output transmission unit 160 for transferring the rising data dinr and the falling data dinf to a global input/output bus GIO in response to the data input strobe pulse dinstbp.
FIG. 2 is a timing diagram illustrating a data input path of DDR SDRAM shown in FIG. 1.
Referring to FIG. 2, in case of the DDR SDRAM, two data are accessed for one cycle period of the data strobe signal DQS. During this, the data DIN entering by being synchronized with the data strobe signal DQS is divided into the rising data dinr and the falling data dinf passing through the data input buffer 130, the rising data latch 141, and the data arranging unit 150, and these data dinr, dinf are transferred to the global input/output bus GIO passing through the global input/output transmission unit 160. The global input/output transmission unit 160 transfers the rising data dinr and the falling data dinf to the global input/output bus GIO in response to the data input strobe pulse dinstbp, and the data input strobe pulse dinstbp is generated by the clock pulse clkp2 when the control signal soseb_wt is applied to the input control signal generation unit 170 shown in FIG. 1.
As aforementioned, the data input strobe pulse dinstbp is constant because of being generated by the clock pulse clkp2 but the data strobe signal DQS is inputted within a predetermined time tDQSSmin to tDQSSmax after inputting a write command WT. In response to this, according to the time tDQSSmin to tDQSSmax inputting the data strobe signal DQS, a margin between the data strobe signal DQS and the data input strobe pulse dinstbp is varied. As a result, it is not correctly performed for a timing of inputting the rising data dinr and the falling data dinf to the global input/output transmission unit 160, and arrangement of those data dinr or dinf and the data input strobe pulse dinstbp, as a command signal for loading those data dinr, dinf to the output bus GIO.
For instance, after the write command is inputted and the tDQSSmax is passed, if the data strobe signal DQS is applied, the data input strobe pulse dinstbp is correctly inputted while the data dinr or dinf is inputted to the global input/output transmission unit 160. As a result, the data dinr or dinf is exactly loaded to the output bus GIO. However, after the write command is inputted and the tDQSSmin is passed, if the data strobe signal DQS is applied, the data dinr, dinf are inputted to the global input/output transmission unit 160 and the data input strobe pulse dinstbp is inputted later. Accordingly, a misalignment A is occurred and a margin for an input operation is reduced. In worse case, the first data input strobe pulse dinstbp is inputted at a timing that the next data is inputted, so that it is impossible to perform a correct data loading.
As described above, as there isn't constant time tDQSSmin to tDQSSmax inputting the data strobe signal DQS after a write command and the data input strobe pulse dinstbp loading the data is constantly generated by the clock signal pulse clkp2, it is difficult to arrange data. Furthermore, if an operation speed is getting fast or if misalignment is getting larger, it causes a failure in transferring data.